In a multi-port device, two signals from the MAC can be shared among multiple PHY chips, while another 16 signals (MII routing) or 6-7 signals (RMII routing) are required per PHY chip. The primary difference between these two routing standards is the number of signals required to interface between the MAC and each PHY chip. Routing between the MAC and PHY follows either the MII or RMII routing standards with point-to-point topology. Normally dog bone fanout is fine the pitch on these components is not super-fine and you'll be able to reach the first two rows of balls on the surface layer (see above). If you're designing a network switch with high port count, the controller ICs may have a BGA footprint, so you'll need an escape routing scheme. Normally, microstrips are used on the surface layer, but striplines can also be used.
Next we need to consider routing between different chips in the system, and to the connectors. All routes within this scheme should be placed on a single layer with precise length matching. Routing uses 50/100 Ohm single/differential impedance, requiring impedance controlled routing over a ground plane. The standard routing protocols for Ethernet (MII and RMII) are compatible with 10Base-T and 100Base-TX, although similar routing standards are designed for 1 Gbps and higher data rates (GMII, RGMII, SGMII, QSGMII, I cover these in the article linked above). If you have an MCU that supports USB but not Ethernet, there are USB to Ethernet data converters that will let you route to an Ethernet port. MCUs that support Ethernet (e.g., Microchip's PIC32 MCUs) will include an integrated MAC/PHY transceiver on the die, giving you a small footprint option. If you're routing an Ethernet port to a processor, you generally won't have dedicated PHY chips or controllers. If you're using this system layout, pay attention to the required MII routing standard between the main controller and the expansion PHY. The expansion PHY chip connects to one of the port outputs using an MII routing standard, and this chip provides the additional ports needed to increase the total port count of the switch. This type of switch controller will typically support about 16 ports. This high port count switch uses a main controller ICM that includes the MAC and integrated PHY layer. The image below shows an example portion of a layout for an Ethernet switch. Take a look at this article to see more guidelines on the various MII standards. However, these other standards, particularly GMII/RGMII, use 125 MHz clock.
In the last point, I've only mentioned MII and RMII, but there are other MII standards that are used in Ethernet routing with that have similar requirements. In RMII, a 50 MHz clock is used for both data rates. In MII, a 2.5 MHz clock is used for 10 Mbps data rates, while a 25 MHz clock is used for 100 Mbps.